1. Field of the Invention
The present invention relates to a layered chip package that includes a plurality of semiconductor chips stacked, and to a method of manufacturing the same.
2. Description of the Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation.
The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; filling the plurality of holes with metal such as Cu by plating to form the through electrodes; and removing unwanted portions of the seed layer.
According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal. This tends to reduce the reliability of wiring formed by the through electrodes.
According to the through electrode method, vertically adjacent chips are physically joined to each other by connecting the through electrodes of the upper chip and those of the lower chip by soldering, for example. The through electrode method therefore requires that the upper and lower chips be accurately aligned and then joined to each other at high temperatures. When the upper and lower chips are joined to each other at high temperatures, however, misalignment between the upper and lower chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the upper and lower chips.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
The manufacturing method disclosed in U.S. Pat. No. 5,953,588 requires a large number of steps and this raises the cost for the layered chip package. According to the method, after a plurality of chips cut out from a processed wafer are embedded into the embedding resin, a plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.
With the multilayer module disclosed in U.S. Pat. No. 7,127,807 B2, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration.
For a wafer to be cut into a plurality of chips, the yield of the chips, that is, the rate of conforming chips with respect to all chips obtained from the wafer, is 90% to 99% in many cases. Since a layered chip package includes a plurality of chips, the rate of layered chip packages in which all of the plurality of chips are conforming ones is lower than the yield of the chips. The larger the number of chips included in each layered chip package, the lower the rate of layered chip packages in which all of the chips are conforming ones.
A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. For a memory device such as a flash memory, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is typically employed so that the memory device can normally function even when some memory cells are defective. The redundancy technique can also be employed in the case of forming a memory device using a layered chip package. This makes it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells has become defective due to, for example, a wiring failure of the control circuit, and the chip cannot function normally even by employing the redundancy technique.
In such a case, the defective chip is no longer usable. While the defective chip can be replaced with a conforming one, it increases the cost for the layered chip package.
U.S. Patent Application Publication No. 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die.
In the case of forming a memory device using a layered chip package, one or more defective chips included in the layered chip package may be identified and access to such defective chips may be disabled in the same way as the technique disclosed in U.S. Patent Application Publication No. 2007/0165461 A1.
Disabling access to a defective chip in a layered chip package, however, gives rise to the following two problems. A first problem is that the defective chip is electrically connected to a plurality of terminals of the layered chip package by wiring, and such a connection can possibly cause malfunction of the layered chip package.
A second problem is that, for a layered chip package that includes a predetermined number of chips and is able to implement a memory device having a desired memory capacity when all the chips included in the layered chip package are conforming, simply disabling access to any defective chip included in the layered chip package is not sufficient for implementing the memory device having the desired memory capacity.